In contemporary semiconductor technology, planar devices are constructed to include trenches which may be used in order to isolate active devices formed within the semiconductor. For example, these trenches may be used in bulk CMOS processes or in silicon-on-insulator (SOI) topologies. Under current technology, conventional trench isolation is performed by photolithography. As a result, the width of the trench formed by the photolithographic process may be no shorter than the resolution of the photolithographic device. For example, in contemporary one micron technology, the width of a trench is necessarily limited to being no shorter than one micron.
The aforementioned limitations associated with photolithography impose particular constraints on SOI MOSFETs. Electrical isolation of SOI MOSFETs is typically achieved through removal or trenching of the silicon-on-insulator layer in the field region. Active device structures are then fabricated in the resulting silicon mesas by standard integrated circuit fabrication methods. While high packing density and total dielectric isolation is achieved by this technique, mesa isolation suffers from poor device topography and difficulty in suppressing the parasitic mesa sidewall transistor.
An additional approach, which allows optimum packing density, planar device topography and high radiation tolerance is to isolate individual device structures by dielectrically filled trenches. Conventional trench isolation of bulk MOSFETs is performed by photolithographically defining the trench opening, etching with an anisotropic silicon etch and refilling the trench with a suitable dielectric material. The trench refill process is normally done in two steps: (1) deposition of a conformal layer of a thickness greater than one-half the trench width in order to completely refill the trench; and (2) anisotropic etchback of the deposited layer to remove the deposited material from non-refilled areas. However, this refill and etchback technique becomes very difficult to control when applied to thin film (0.3 microns) SOI MOSFETs. The difficulty arises because the aspect ratio, that is the ratio of the trench depth to the trench width, may no longer be optimized. In particular, this aspect ratio is preferably on the order of 10 to 1. Thus for a 0.3 micron deep trench, a trench width on the order of 0.03 microns is desirable; however, under standard one micron photolithography, there exists no method for forming a trench having a width under one micron. As a result, standard photolithographic processes may not be used to create trenches for thin film SOI applications.
Therefore, a need has arisen for a method and structure for forming a trench within a semiconductor layer of material without having to rely solely on photoliphographic processes in order to define the width of the trench formed.